For many applications, such as system-on-chip, it is desirable to integrate logic devices and interface circuits based upon metal-oxide-semiconductor (MOS) field-effect transistors and non-volatile memory (NVM) transistors on a single chip or substrate. This integration can seriously impact both the MOS transistor and NVM transistor fabrication processes. MOS transistors are typically fabricated using a standard or baseline complimentary-metal-oxide-semiconductor (CMOS) process flows, involving the formation and patterning of conducting, semiconducting and dielectric materials. The composition of these materials, as well as the composition and concentration of processing reagents, and temperature used in such a CMOS process flow are stringently controlled for each operation to ensure the resultant MOS transistors will function properly.
Non-volatile memory (NVM) devices include non-volatile memory transistors, silicon-oxide-nitride-oxide-semiconductor (SONOS) based transistors, including charge-trapping gate stacks in which a stored or trapped charge changes a threshold voltage of the non-volatile memory transistor to store information as a logic 1 or 0. Charge-trapping gate stack formation involves the formation of a nitride or oxynitride charge-trapping layer sandwiched between two dielectric or oxide layers typically fabricated using materials and processes that differ significantly from those of the baseline CMOS process flow, and which can detrimentally impact or be impacted by the fabrication of the MOS transistors.
In particular, forming a gate oxide or dielectric of a MOS transistor can significantly degrade performance of a previously formed charge-trapping gate stack by altering a thickness or composition of the charge-trapping layer. At 28 nm and beyond, CMOS technologies will switch to using a thin High-k dielectric in place of the silicon dioxide or silicon oxynitride and metal gate instead of polysilicon. The process flow for these elements is significantly different than the current CMOS and NVM process flows. In addition, this integration can seriously impact the baseline CMOS process flow, and generally requires a substantial number of mask sets and process steps, which add to the expense of fabricating the devices and can reduce yield of working devices.